Tag: Network-on-Chip
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Reviving this blog … with a question about binary trees
Work changes and a determination to actually finish my PhD mean I really should make a bit of an effort here and so I will. Here is a puzzle that has been bothering me about binary trees which has come from my PhD research… In that research I am investigating how to implement virtual memory […]
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Reaching a decision
A week further on and not much C++ has been written – and now I think I need to make a new start. Up to this point I have been trying to write a software model of the hardware and my thought was I could think put a software-modelling layer on top of that. But […]
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Further thoughts on the simulation task
Lying in bed this morning and puzzling over what to do … At first I thought what I should do is copy one of the existing operating system models for NoCs, but that simply would not be flexible enough. What I have to do is model the hardware (including the modifications to the MMU I […]
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How much memory do you need?
What’s the best way to speed up your computing experience? As many know the most cost-effective way is often not to buy a new computer with a faster processor but to add more memory to an existing system. The plot below, based on some results from my PhD research shows just how this works… In […]
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Going atomic … or concurrency is hard
In my PhD world a year’s worth of software experimentation has proved what we all knew already … that systems using traditional memory models struggle in the Network-on-Chip environment and so I am now trying something slightly different. My “model” (it’s all in software) is of a 16 core system, with each core having a […]
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Curses on ncurses
Every programmer will be familiar with something like this… A little while back I wrote a program that simulates – crudely but effectively – a multicore NoC device. I use it to model the execution times of different page replacement algorithms. The input is XML generated via a step by step trace of a working […]
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Traffic generation options
This is a blog post where I am going to write about things as a way of clarifying, in my own mind, what the best way of tackling a problem is. So far, in research for my PhD, I have concentrated on establishing some base points for potential performance of Network-on-Chip systems running multithreaded code. […]
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After paging?
Paging and virtual memory is at the heart of just about any computing device – more complex than a DVD player – we use everyday. Paging is the memory management system based on the idea that we can divide the real memory of our computer into a sequence of smallish (typically 4,096 bytes) of “page […]
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None of the easy things work
This is a post about my PhD research: in fact it is a sort of public rumination, an attempt to clarify my thoughts in writing before I take the next step. It’s also possibly an exercise in procrastination: a decision to write about what I might do next, rather than to get on with doing […]
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Looks like one hope/theory knocked on the head
Now I have mapped the speed of OPT and LRU using a traditional two level memory hierarchy, my task is to find something better that might make NoC a more viable computing platform. One thought that occurred to me was that the preference of C and similar languages for page aligned memory in certain situations […]
cartesian product ... stuff about computing mostly 