A RISC-V single board computer

I finally have a RISC-V based single board computer (SBC) – the Nezha from RV Boards shipped to me directly from China.

It’s tiny (about the same form-factor as a Raspberry Pi though) and relatively expensive (it cost me just over £100 to order and get it shipped here) but whilst I was slightly concerned I was being a bit naïve in buying it (as it was either a scam or it wouldn’t work), it boots (slowly) into Linux (see image) and works (slowly).

Can RISC-V cores (which are ‘open source hardware’ and free from licensing fees) break ARM’s grip on SBCs and similar devices? A year ago the answer looked like a very clear negative as, despite years of hype, RISC-V designs just weren’t moving off the page and into silicon. Now it looks much more uncertain as the Nezha is actually the second RISC-V SBC to ship (the other, the Beagle-V, has only been distributed to a select group of developers so far – and this didn’t include me despite my application – but is expected to be available globally in the autumn).

The plans are for RISC-V SBCs retailing for less than $20 inside a year and – crucially – for the RISC-V cores to feature vector extensions which could mean some interesting use-cases being opened up.

(If you want to know more about RISC-V or if you are thinking of starting a RISC-V assembly project I cannot recommend The RISC-V Reader highly enough.)

Right now I am trying to get Riscyforth to run on my machine.


4 responses to “A RISC-V single board computer”

  1. The RISC-V architecture is open — you don’t need to pay anything to use the specification.

    Some “cores” are open too. I think that these are: https://www.openhwgroup.org/projects/

    Possibly the best cores, eg. from SiFive, are not free.

    Your board is not using an open core. It uses an Allwinner D1 chip which has a core licensed from Alibaba (as far as I can tell).

    Even if a design uses an open core, you still have to find a bunch of other bits of the puzzle: PCI, USB, Ethernet, power management, etc.

    I think that Seagate and WD are shipping things with in-house RISC-V SoCs. In tremendous volumes. NVidia was interested but they seem to be buying ARM itself instead. Bloomberg says Intel has made an offer for SiFive.

    As much as I like RISC-V, it isn’t important for programmers. These days we can use any good-enough architecture, pretty much interchangeably. Competition will improve each of these choices.

    1. Thanks for the comment. Pithy and informed as always!

      I guess part of this is about what I mean by a “core” and for the avoidance of doubt I really meant the CPU rather than any of the other things that might be on the silicon die with it. The users (ie hardware manufacturers) of the RISC-V designs aren’t paying a licence fee, though that is probably only a small part of any computing device’s cost (though a bigger proportion at the cheaper end, surely) but, as you suggest, they could be placing lots of other proprietary things in their SoCs.

      RISC-V based designs are being used in lots of mass produced low end devices – presumably because the lower cost matters here, but the difference here is that this is a device in the Raspberry Pi space of users who aren’t necessarily going to be willing to use a null modem cable to get the output. I hope that the drive to make lower cost RISC-V SBCs succeeds because it would be good to have more devices out there doing more things.

      Most programmers use abstractions from assemblers to DSLs to get away from the CPU architecture, but I think it still matters – not least because if we ended up in a world where there were only ARM cpus then there wouldn’t be much competition – and I worry a little that we are heading that way.

      1. The last paragraph of my comment matches the last comment of your reply. I’m glad you made it more clear.

        “core” feels a little ambiguous to me, so I’ll try to be a bit more explicit. Note: I’m not really a hardware guy.

        Making a processor has a stack of tasks, often performed by different entities, with different forms of compensation.

        There’s the architecture. Under what terms can you use an architecture? In the case of RISC-V (and, I think, SPARC before it), you can use it with no payment to the “owners”.

        There’s the selection of options. For example, ARM seems to charge more for options. (I’m sad that the Raspberry Pi Foundation (or maybe Broadcom) didn’t pay for the cryptographic extensions from ARM.) RISC-V: free. (I feel that RISC-V’s options are too many and too fine-grained, leading to fragmentation.) (Some important options are not getting ratified in a timely manner.)

        There’s creating the logic for a processor. This is essentially software describing the circuitry. A typical language would be System Verilog, a “register transfer language”. It could be designed for an FPGA or a fully-custom IC. For RISC-V some are free, many are not.

        An FPGA implementation is great for prototyping. The performance or cost hit is hard to justify for anything else.

        There’s creating the final circuit design. I don’t know what that looks like, but it includes layout and power distribution and more. Perhaps designing each mask is a different step. This is unlikely be free.

        There’s fabricating, dicing, bonding, and packaging of chips. This won’t be free.

        I don’t imagine Allwinner does any packaging. I don’t know how much of the other steps they did; perhaps all were supplied by Alibaba Xuantie 910.

        Cutting edge fabrication can only be done in one of a very small number of fabs. But the Allwinner D1 is probably using design rules / density suitable for very old fabs. There are more of those available.

  2. Ah, right I get your competition point now: I thought you meant the competition was essentially a given.

    Yes, the lack of capacity in actually making these things is a big bottleneck – the industry has become too concentrated possibly, a consequence of the very large outlay required to build the fab plant versus the risk of zero or less than zero return. Whether RISC-V fixes that is, as I think you are saying, very far from guaranteed.

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