This, dismally crude (sorry), drawing shows how it is done for the simplest type of CRC – a parity bit. This arrangement calculates an even parity bit (ie it ensures that the bit stream transmitted always contains an even number of ones).

The parity bit will be set to 0 if the input has an even number of 1 bits and 1 if it has an odd number of 1s: here is how it works (the gate is a XOR gate).

As this is a CRC the parity bit is originally set to 0. So for input 1011 we have:

(input bit) 1 XOR (parity bit) 0 = (final state of parity bit) 1

0 XOR 1 = 1

1 XOR 1 = 0

1 XOR 0 = 1

(so in this case the bit is set to 1)

And for 100111 we have:

1 XOR 0 = 1

0 XOR 1 = 1

0 XOR 1 = 1

1 XOR 1 = 0

1 XOR 0 = 1

1 XOR 1 = 0

So, as the input already has an even number of bits then the parity bit would be set to 0.

This is the equivalent of a CRC generator polynomial of . A parity bit will catch the switching of one (or any odd number) of bits but will fail to detect errors for any even number of bit switches, so it is of some, but limited, use.

For bigger generator polynomials a similar arrangement is used – with more bits where the parity register is (see Computer Networks and Internets).

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